The invention described herein was made in the performance of work under a NASA contract, and is subject to the provisions of Public Law 96-517 (35 USC 202) in which the Contractor has elected to retain title.
The present disclosure is directed to active pixel sensors, and more particularly to multi-resolution active pixel sensor array imagers for light adaptive imaging applications.
The CMOS active pixel sensor (xe2x80x9cAPSxe2x80x9d) has permitted the realization of high performance products. Each pixel has an active amplifier that buffers the photosignal. A column-parallel bus readout architecture is often used. In this architecture, the columns are connected to individual signal processing modules, which include, for example, A to D converters, and double sampling elements.
A constant challenge in smart imager technology continues to be how to enhance signal to noise ratio (xe2x80x9cSNRxe2x80x9d) under low illumination conditions.
One way to do this is to trade spatial resolution for SNR by summing neighborhood pixels (pixel binning). A CMOS imager that averages signals from a neighborhood of pixels has been demonstrated in xe2x80x9cProgrammable Multiresolution CMOS Active Pixel Sensorxe2x80x9d, in Solid-state Sensor Arrays and CCD Camera, Proc. SPIE vol. 2654, pp. 72-81, 1996, by Panicacci, et al.
A CMOS imager with frame memory and pixel binning has been demonstrated in a reference titled, xe2x80x9cFrame-transfer CMOS Active Pixel Sensor with Pixel Binningxe2x80x9d, special issue on Solid-State Image Sensors, IEEE Trans. On Electron Devices, vol. 44 (10), pp. 1759-1763, 1997, authored by Pain, Zhou and Fossum.
The present disclosure is directed to an improved pixel- binning imager. In accordance with a preferred embodiment, the imager may be easily configured to provide an imager having multi-resolution capability where SNR can be adjusted for optimum low-level detectibility.
Further in accordance with the preferred implementation, multi-resolution signal processing functionality is provided on-chip to achieve high speed imaging, as well as low power consumption.
An imager architecture described preferably has an improved pixel binning approach with fully differential circuits situated so that all extraneous and pick-up noise is eliminated. Unlike the frame-transfer APS with pixel binning, the current implementation minimizes the necessary memory, thereby reducing chip size. The reduction in area enables larger area format light adaptive imager implementations.